FIGS. 1(A) and 1(B) show an example of the wiring structure of a conventional Master-Slice LSI. In FIG. 1(A), the numeral 1 indicates a LSI chip composed of a semiconductor substrate. The numerals 2a to 2f indicate gate cells produced in the semiconductor substrate 1. The cells, including silicon-gate MOS transistors or the like, are arranged at predetermined positions and have logic functions. The gate cells 2a to 2f constitute blocks including circuit components, wherein the blocks are provided separately from each other. The numerals 3 and 5 in FIG. 1(B) indicate terminals of the gate cell 2b, and the numeral 4 indicates a terminal of the gate cell 2a. The numeral 6 indicates an imaginary wiring grid established in the wiring region 7 between the gate cell 2a and 2b. The numerals 8 and 9 indicate horizontal wirings along the horizontal lines of the wiring grid 6, both of them comprising a horizontal wiring layer. The numerals 10 to 12 indicate vertical wirings along the vertical lines of the wiring grid 6, all of them comprising a vertical wiring layer formed on an insulating layer (not shown) which is formed on the horizontal wirings 8 and 9. The numerals 13a, 13b, 13c indicate through holes for connecting between the horizontal wiring and the vertical wiring, provided in the insulating layer which is provided between the horizontal and the vertical wiring layer. The vertical and the horizontal wiring layer can be made as a first and a second layer respectively.
In the conventional Master-Slice LSI shown in FIG. 1, wiring is conducted by providing the horizontal wiring 8 and the vertical wirings 10, 11, and providing the through holes 13a and 13b in the insulating layer so as to connect between the terminals 3 and 4 which lie in the same plane of the LSI chip 1 and should be in equal electric potentials. In this case, permissible minimum intervals between the horizontal wirings and between the vertical wirings are determined beforehand caused by a restriction in view of manufacture. So, in this conventional system, it is possible to conduct wiring with considerable ease by an automatic wiring using the imaginarily wiring grid 6 so as to have the permissible minimum intervals described above.
However, there arises a restriction (hereinafter referred to as an "vertical constraints") that the horizontal wiring (hereinafter referred to as a "trunk line") 9 which is to be connected to the upper terminal 5 must be arranged above the trunk line 8 which is to be connected to the lower terminal 4 in order to avoid a short-circuit between the vertical wirings (hereinafter referred to as a "branch line") in a case where the terminals 5 and 4 are located on the same vertical line of the wiring grid 6.
Accordingly, in Master-Slice LSIs, wiring may become quite difficult with the increased number of gate cells because the height of the wiring region 7 between upper and lower gate cells is predetermined. Herein, the height of the wiring region 7 corresponds to the number of horizontal lines of the wiring grid 6.
Furthermore, in FIG. 2, in a case where the terminals 14a and 14b, 15a and 15b are to be connected with each other respectively, and the terminals 14a (or 14b) and 15b (or 15a) are located on the same vertical line of the wiring grid, wiring becomes more difficult caused by the above-mentioned vertical constraints. In greater detail, it is impossible to connect the terminals 14a and 14b and the terminals 15a and 15b by only three wirings respectively in the same manner because if it is tried at least one of the three wirings connecting the terminals 15a and 15b would cross with one of the three wirings connecting the terminals 14a and 14b on the same level.
In such a case, the incapability of wiring caused by the vertical constraints is conventionally resolved by dividing a trunk line into a few pieces as shown in FIGS. 3(A) to (C). In FIGS. 3(A) to (C) the terminals 14a and 14b are connected by three wirings, that is, two vertical wirings 21, 22 and a horizontal wiring 23. On the other hand, the signal terminals 15a and 15b are connected by five wirings, that is, three vertical wirings 24, 25, 26 and two horizontal wirings 27, 28.
However, in a case shown in FIGS. 3(B) and (C), there are disadvantages in that the whole length of the wiring will increase, resulting in increased signal transfer time, and that a new-type difficulty in wiring will arise because the entire wiring 25 and a part of wirings 27, 28 are located outside the rectangular region surrounded by the four terminals 14a, 14b, 15a and 15b. Furthermore, even in the case of FIG. 3(A), there remains a problem that wiring will become difficult with the increased number of gate cells.